The present invention relates to coherent imaging systems using vibratory energy, such as ultrasonic or electromagnetic waves, and, more particularly, to a novel method and novel apparatus, for digital beam formation by delayed sampling and digital baseband demodulation. Our method utilizes a non-uniform clock to capture received waves in either a single high-speed analog-to-digital converter (ADC), or a plurality K of lower speed ADCs; after ADC sampling, the digital signal undergoes digital baseband demodulation in a two-stage demodulator which is followed by FIR filters and decimators to provide baseband signals at a much lower rate than the equivalent ADC clock rate.
A method and apparatus for fully digital beam formation in a phased array coherent imaging system, such as an ultrasonic medical imaging system and the like, is described and claimed in now-allowed co-pending application, Ser. No. 944,482, which was filed on Dec. 19, 1986, and is incorporated herein in its entirety by reference. The imaging system utilizes a phased array sector scanner (PASS) to rapidly and accurately sweep a formed beam of vibratory energy. The desired beam pointing accuracy is obtained by maintaining an accurate set of phase relationships, which are, in fact, a set of time delays between the various N transducer elements of the PASS array. By decoupling the required phase accuracy and time delay accuracy from one another, the signals can be coherently summed with great accuracy. However, in order to preserve both the amplitude resolution and the time resolution necessary for proper beam formation, the analog-to-digital converter (utilized for converting the analog signal from each channel transducer, at any instant, into a digital data word for processing) must carry out conversions at a sample frequency of at least two times, and usually four times, the maximum operating frequency of the imager. This requires the use of an 8-bit, 40 MHz ADC for each of the N channels (where N is on the order of 64) of an ultrasonic medical scanner; the integrated circuit chip area necessary, even utilizing VLSI implementation, is prohibitive, as is the cost. Additionally, operating at such a high sampling rate requires that a relatively large amount of high-speed random access memory be utilized to store data so that a realistic amount of steering-angle time delay can be provided in each of the N channels, prior to coherent summation across those N channels of the array. For example, if about 10 microseconds of total time delay must be obtained prior to coherent summation, an ADC sampled at 40 MHz must be accompanied by at least 400 words of high speed RAM for required data delay in each of the N channels. It is highly desirable to also reduce the operating speed and required depth of the channel time-delay RAM memory.